1. Field of the Invention
The present invention relates to a dynamic address translation system, particularly to a dynamic address translation system in a channel or sub-system adapter in which the main memory is used in common with the central processing unit.
2. Description of Prior Art
In channel dynamic address translation systems in existing data processing systems, page fixing processing is conducted prior to the accessing of the main memory by the channels. In order to allow the access to this fixed page by the channels, the channel invalid bit is made OFF and thereafter the SIO instruction is issued for allowing access by the channels. These page fixing processes and the channel invalid bit operation are controlled by the operating system. However, this system has problems in that the overhead for searching the page to be fixed is applied also to any input/output devices to be connected to channels prior to the execution of channel programs, and the number of pages being fixed increases while starting a number of input/output devices, thereby causing the real memory to run short.
Moreover, in channel dynamic address translation systems in existing data processing systems, access protection for the main memory has been performed by comparing the storage key in every physical page within the main memory and the channel key to be transferred to channels while the SIO instruction is issued. In the virtual memory system, the access protection should naturally be performed in a unit of logical data. However, this system has problems in that the logical access protection data should be mapped to the physical access protection mechanism, causing an archtectural illogicality in that the channel must recognize the logical addresses for address and the physical keys for access protection. Furthermore, the overhead of mapping is also applied.